FPGA+Firmware


 * __FPGA Firmware__**

The general overview of the FPGA subsystem is shown in Figure 7.0.1 Figure 7.0.1 – FPGA Block Diagram (High Level) Basically, the system needs to down-convert the incoming 1 MHz bandwidth down to baseband. So, the system is mixed with 19.6 MHz, such that the incoming spectrum starts at DC. Then, it is low-pass filtered to remove the image component (which will exist at 39.7 MHz). Then, the signal is CIC filtered to decrease the system sampling rate to a level that can actually be transmitted over USB. A data rate of 20 MB/s was desired for the USB controller. However, the signal was translated into I and Q components, and each of those had to be transmitted a byte at a time (with a 2-byte signal sampled on each clock cycle). Therefore, signal was decimated by a factor of 20. Since the clock rate was 100 MHz, this resulted in a final sampling rate of 5 MHz. However, when the signal was time-division multiplexed for each byte of both streams (2 bytes per stream), the final sample rate of the signal entering the USB controller was 20 MHz. System Generator was used to generate an HDL netlist based on a block diagram of the system, and then Xilinx was used to synthesize and map the system onto the FPGA.

Mixing
The first section in the system is the mixer. The mixer uses a ROM to store a sine wave with 19 bits of accuracy. The next step is to send it through a multiplier. For the purposes of this project, the embedded multipliers were used since they are not implemented in the filters.

 Figure 7.1.1 – Mixer Block Diagram

Next, the system was low-pass filtered. Since the image component is so high, the cutoff frequency was set at 20 MHz to relax the filter specifications. Since the cutoff frequency was not such a small fraction of the sampling frequency, the filter could achieve a good attenuation at 39 MHz while keeping the amount of resources consumed by the FPGA low enough that the rest of the system could be implemented. The filter magnitude response is shown in Figure 7.1.2.

 Figure 7.1.2 – Post-Mixer Low-Pass Filter (16 tap FIR, fs = 100 MHz) The filter was implemented using a distributed-arithmetic architecture, and was structured in such a way that it was completely parallel. Since at this point in the system, the signal has not been down-sampled, this is a necessity. Finally, the filter output is recast in such a way that the normally 36 bit output becomes 16 bit with a binary point at the 14-th bit. The system output with a 20.1 MHz input test signal was simulated, and the results are shown in Figure 7.1.3 (in analog waveform view) and in Figure 7.1.4 (in logical view to get a sense of the timing).  Figure 7.1.3 – Mixer Output Simulation (Analog)

 Figure 7.1.4 – Mixer Output Simulation (Logic)  The results show that the sampled input signal has been successfully downconverted to 1 MHz at a parallel rate (the clock rate is 100 MHz).

Decimation Stage 2
The signal was decimated again by a factor of 5, thus bringing the sampling rate down to 5 MHz. This stage of the FPGA block diagram takes the same basic structure as the first decimation stage: there is a downsampling block, followed by an FIR filter, and finally the signal is recast back to a 16-bit width. The FIR filter at this point could theoretically be serialized to a high degree. The two input signals are multiplexed in the filter block, which reduces the overall available clock cycles for each stage by a factor of two. However, that still leaves 10 clock cycles to compute the filtering operations for 16 bits of data. In the actual implementation, this filter was left as a completely parallel filter with a multiplexed input. However, there is the possibility of serialization, which would //theoretically// greatly reduce FPGA resource consumption while maintaining system throughput. The FIR filter magnitude response is shown in Figure 7.3.1. Figure 7.3.1 – Filter Magnitude Response (6 Tap FIR, fs = 5 MHz) The system output up to this point was simulated, and the results are shown in analog form (Figure 7.3.2) and in logical form (Figure 7.3.3).  Figure 7.3.2 – Decimation Stage 2 Output (Analog)  Figure 7.3.3 – Decimation Stage 2 Output (Logical)

Time-Division Multiplexing
<span style="display: block; font-family: 'Times New Roman','serif'; font-size: 16px; text-align: left;">For the penultimate section of the FPGA block diagram, each of the two 16-bit streams are split into two 8 bit streams. Then, the 4 streams are time-division multiplexed. So, the four streams are transmitted in the time it would normally take to transmit one of them. So, the sampling rate increases by a factor of 4 (from 5 MHz to 20 MHz). Since there is a byte of data transmitted on every 20 MHz clock cycle, the overall data-rate going to the USB is 20 MBps. The block diagram is shown in Figure 7.4.1. <span style="display: block; font-family: 'Times New Roman','serif'; font-size: 16px; text-align: center;"> Figure 7.4.1 – Time Division Multiplexing Block Diagram

<span style="font-family: 'Times New Roman','serif'; font-size: 16px;">The system output up to this point was simulated. Only the logical implementation will be shown since it is most useful to see the bit-latch timing (Figure 7.4.2).

<span style="display: block; font-family: 'Times New Roman','serif'; font-size: 16px; text-align: center;"> Figure 7.4.2 – Simulation of Time-Division Multiplexed Output

USB Control
<span style="display: block; font-family: 'Times New Roman','serif'; font-size: 16px; text-align: left;">The USB controller was written as a transmit-only interface. The data is latched onto the data bus of the Cypress FX2 chip on the rising edge of the 20 MHz clock. The USB control lines on the Cypress FX2 chip are controlled from this module. Three onboard LED’s on the Nexys board are also used to show the status of the transmission and endpoint buffer. The block diagram is shown in Figure 7.5.1. <span style="display: block; font-family: 'Times New Roman','serif'; font-size: 16px; text-align: center;">Figure 7.5.1 – USB Control Schematic Symbol

<span style="display: block; font-family: 'Times New Roman','serif'; font-size: 16px; text-align: left;"> The full system output was simulated, and the results are shown in Figure 7.5.2.

<span style="display: block; font-family: 'Times New Roman','serif'; font-size: 16px; text-align: center;"> Figure 7.5.2 – USB Controller Simulation