Power+Board

__**Power Board**__

The next board to discuss is the power board. This board was designed to supply the RF Front End board and the ADC board.

Distribution and Protection
The expected current load of each subsystem (determined through prototype testing) is summarized in Table 5.1.1.

Table 5.1.1 – Sub-circuit Current Draw  The current was distributed through two main paths. The first path was designed to supply the RF front end board, the second path was design to supply the ADC.

Figure 5.1.1 – Distribution Path Both paths begin with a 12V regulator to step down the input voltage to a common 12V level. In practice, a 13.5V supply was used for all testing and initial prototyping. However, in theory, any voltage from slightly above 12V to 18V could be used as a supply. The assembly itself allows the user to attach a standard 2.1 mm barrel plug for power, and it also has banana plug jacks for battery or auxiliary power.

The main source of power-supply protection is protection from excessive current. Two parallel PTC’s are placed in series with the input supply rail. Whenever the current exceeds 1.5A, the PTCs will trip and the input will open. The power line will be restored once the system is reset.

Regulation
The power system uses low dropout regulators exclusively for voltage regulation. Although switching regulators are generally more favorable because of their high efficiency, LDO’s were necessary in this application because of the switching noise that would contribute to the overall noise floor is switching regulators were used. LDO’s typically have much better noise performance. Standard adjustable regulators were used (see Figure 5.2.1) Figure 5.2.1 – Standard Adjustable LDO Circuit

Low-Noise Augmentation
The noise performance of the LDO circuit can be further improved. The idea for this improvement came from an application note from Maxim Integrated Circuits. Maxim Integrated Circuits “Single Transistor Reduces LDO Noise by 46 dB”

Using a simple RC low-pass filter and a Darlington transistor, one can reduce the noise density of the LDO considerably, which will of course reduce the overall noise voltage. The filter is designed with a very low cutoff frequency. Typically, the noise voltage density for LDO’s will be very high in the kHz range, and will die off such that it is virtually nonexistent at frequencies greater than 1 MHz. The filter allows further attenuation of this low frequency noise, thus reducing the noise voltage density. For the transistor, high gain transistors are preferred, because then the base current requirement for the proper load current is decreased. Furthermore, transistors with high Early voltages should be used, since such transistors reject noise at their base. The typical configuration using the LT1086 to step down 12V to 6V is shown in Figure 5.3.1. Figure 5.3.1 – Typical Configuration In the case of the system power circuit, typically third-order pi-configuration low pass filters were used. The resistor had to be chosen to allow as much current to flow to the base of the transistor as possible, to get the full current to pass through the transistor from the input path. Thus, the capacitors needed to have fairly high capacitances to keep the cutoff frequency low. Also, the resistance values to adjust the voltage vary from those specified by the datasheet. Although the noise is lowered considerably with this circuit, the load regulation suffers. Simulation results were used to tune the voltage outputs such that they would vary within an acceptable degree within the calculated current demand variations.