ADC+board

__**ADC Board**__

The analog digital converter (ADC) is an important part of the system. The ADC has to convert the analog input signal into a digital signal that can be processed by the PC. The ADC accomplishes this by sampling the incoming continuous analog signal into a discrete digital signal. The sampling rate of the ADC must be chosen so that it is high enough to sample the sinusoidal waves that will be coming through the input. In the frequency domain, the sampled signal is the convolution of the spectrum of the original signal and the impulse train (comb function). Therefore, there will be spectral copies of the original spectrum at every integer multiple of the sampling frequency. This is illustrated in Figure 6.1

 Figure 6.1: Spectrum of a Sampled Baseband Signal

 If the signal is sampled too slowly, aliasing will occur. When aliasing occurs, the spectral copies of the sampled signal bleed into each other, thus making it impossible to reconstruct the signal later. The Nyquist Theorem can be used to determine how fast the signal should be sampled to avoid this. It states that the sampling frequency should be at least twice as high as the highest frequency that the signal contains.

 Often, it is sufficient to sample at exactly twice the highest frequency contained in the baseband signal. However, with sinusoids, some issues occur when this is attempted. Sine functions have the same value when they are sampled at the start of their period, halfway through their period, and at the end of their period. In order to capture a representative sample of the behavior of a sine wave, a higher sampling rate must be used. A sampling rate of 8 or 16 times the highest frequency would yield a more accurate representation.

Dynamic Range and Resolution
Dynamic range is defined as the ratio between the largest and smallest possible signals the receiver is able to detect. The dynamic range of the receiver was desired to be approximately 100dB. The dynamic range of an analog to digital converter with N-bit uniform quantization is defined by:  A 16-bit ADC would have an ideal dynamic range of 96.3dB however we cannot treat this as ideal and the goal of a 100dB of dynamic range is already out of reach. The data sheet for the AD9460 publishes a value for the effective number of bits at several different frequencies and by using this number it is possible to treat a non ideal 16-bit ADC as an ideal 12.7-bit ADC resulting in a dynamic range of 76.46dB.

 The value for the effective number of bits is also very helpful in determining the resolution of an ADC. When the reference voltage is set to 3.4V, the largest value that can be input is 1.7V on a single analog input. The resolution of this ideal 12.7-bit ADC is equal to the reference voltage divided by the total number of quantizational levels. From this resolution we can calculate the minimum amount of gain required for the system to be able to measure and record microvolt level signals. The AD9460 uses differential analog inputs which effectively double the signals peek-peek voltage. This is primarily done to remove any common mode noise present in both signal paths to improve the overall performance of the ADC. As an example, when 1µV is applied on a single analog input, the difference will result in a 2µV peek-peek signal. Since the resolution of the ADC is 510µV and an analog input of 1 µV results in a 2µV signal, a minimum gain of 256 or 48dB is required, and this will just allow the signal to be detected. By multiplying our lowest desired signal, we have also effectively reduced our upper limit by the same amount. By applying 48dB of gain we can theoretically detect a 1µV level signal but the maximum input signal per analog input has now been reduced from 1.7V to 6.64mV. In the final design, the RF front end provides the system with 57dB of gain, which amplifies a single 1µV input to 0.708mV or 1.41mV differentially and reduces the maximum input to 2.40mV single ended or 4.80mV differentially.

AD9460 Development board
 For this project we selected the AD9460 development board as the ADC platform of choice. The AD9460 is a 16-bit, 105 MSPS, with a selectable 2.0 t0 4.0V p-p full scale differential input. It can also be configured for LVDS or CMOS outputs. The development board comes preconfigured to output LDVS but also implements a conversion from LVDS to TTL for the FPGA to sense the level of each bit.

 The reference voltage of the ADC can easily be adjusted by populating two resistors on the board to properly bias the voltage seen by the sense pin. For our application, we wanted to utilize the entire 3.4V span. This was achieved by tying the sense pin to analog ground.

 The AD9460 also offers the ability to choose the data format that is output. There are two different formats, twos compliment and offset binary. The properties of the two coding schemes can be seen in Figure 6.2. The different formats are easily selectable on the development board by adjusting the DFS jumper to either high for twos compliment or low for offset binary. For this project the DFS jumper has been placed in the low position selecting offset binary.  Figure 6.2: Digital output coding

Duty Cycle Stabilization
The development board also has optional duty cycle stabilization circuitry. Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, can be sensitive to the clock duty cycle. Commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9460 contains a clock duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with an approximate 50% duty cycle. Noise and distortion performance are nearly flat for a 30% to 70% duty cycle with the DCS enabled. The DCS circuit locks to the rising edge and optimizes timing internally. This allows for a wide range of input duty cycles at the input without degrading performance. Jitter in the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates of less than 30 MHz nominally. The loop is associated with a time constant that should be considered in applications where the clock rate can change dynamically, requiring a wait time of 1.5 μs to 5 μs after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. During the time that the loop is not locked, the DCS loop is bypassed, and the internal device timing is dependent on the duty cycle of the input clock signal. In such an application, it can be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance. For this project the DCS was connected to analog ground, enabling the duty cycle stabilization.

Clocking the ADC
The AD9460 input sample clock signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Maintaining 16-bit accuracy places a premium on the encode clock phase noise. SNR performance can easily degrade by 3 dB to 4 dB with 70 MHz analog input signals when using a high jitter clock source. For optimum performance, the AD9460 must be clocked differentially. The sample clock inputs are internally biased to ~1.5 V, and the input signal is usually ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. Power supplies for clock drivers were separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. The development board was designed to allow an external clock source to be mounted directly to the board in a DIP-14 package layout in the same location as the SMA connectors. A board was designed to fit the footprint of the DIP-14 package. The oscillator used was the CCHD-950-50-100 which is a 3.3V, 100MHz, CMOS oscillator with a typical RMS jitter of 0.5ps, and phase noise floor of -165dBc. This is an extremely high quality oscillator and has the performance that is desired in clocking high speed data converters. The power to the oscillator was supplied by adding a jumper connecting 5V to XTAL. A 3.3V LDO was used to regulate the 5V down to the oscillators operating voltage. In addition to this clock board, a polarized 0.1uF decoupling capacitor was soldered in place between the signal path and analog ground. The clock signal is then decoupled and split into a differential signal using a RF transformer.

SFDR Option
 Under certain conditions, the SFDR performance of the AD9460 improves by adding some additional power to the core of the ADC. The SFDR control pin is a CMOS-compatible control pin to optimize the configuration of the AD9460 analog front end. Connecting SFDR to AGND optimizes SFDR performance for applications when analog input frequencies are less than 200 MHz. For applications with analog inputs are greater than 200 MHz, this pin should be connected to 3.3V for optimum SFDR performance; power dissipation from AVDD2 increases by approximately 20 mW. For this project, the jumper was positioned so that the SFDR pin is connected to analog ground.

Analog Inputs
It is strongly recommended that the analog input to the AD9460 be differential. Differential inputs improve on-chip performance because signals are processed through attenuation and gain stages. Most of the improvement is a result of differential analog stages having high rejection of even-order harmonics. There are also benefits at the PCB level. First, differential inputs have high common-mode rejection of stray signals, such as ground and power noise. Second, they provide good rejection of common-mode signals, such as local oscillator feed through. The specified noise and distortion of the AD9460 cannot be realized with a single-ended analog input. The AD9460 analog input voltage range is offset from ground by 3.5 V. The analog input voltages are limited by reference voltage selected. The voltage on each input can only have a peek voltage of half the reference voltage. The internal bias network on the input properly biases the buffer for maximum linearity and range. The method used for driving the analog inputs of the AD9460 is using an RF transformer to convert single-ended signals to differential signals. Series resistors between the output of the transformer and the AD9460 analog inputs help isolate the analog input source from switching transients caused by the internal sample-and-hold circuit. The entire signal path has been impedance matched to 50Ω to maintain the quality and power of the signal.

Powering the ADC
<span style="display: block; font-family: 'Times New Roman','serif'; font-size: 16px; text-align: left;">To power the ADC there are two options one from the RF frontend closure and the other from a wall transformer. It is recommended that when the system is being operated for an extended period of time or if there is access to a wall outlet that the ADC be powered from the provided wall wart. The power board is capable of handling the full 1.5A load but is limited on its ability to dissipate heat. The PTC’s will keep the power board from thermal runaway due to excessive current caused by self heating, but the performance of the system may be effected. For this reason it is recommended that when the receiver is not in use, disconnect the signal cable from the ADC/FPGA enclosure and disconnect the power. It is important that the ADC be powered before the antenna is connected. There is a PTC at the output of the RF frontend to limit the current seen by the analog inputs of the ADC, but if the ADC is not powered the protective biasing circuitry is not operational and a strong signal at the inputs could damage hardware.